- May 17, 2015
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Paul Fertser authored
Change-Id: Ibeb9078d19023b8cae5c0371079d5e4e1b5e3c57 Signed-off-by:
Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2776 Tested-by: jenkins
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Paul Fertser authored
Even though the latest firmware version for stlink-v1 supports "v2" JTAG API, the hardware SRST handling is still broken; amend the check accordingly. Change-Id: I62c662cd7aa209d2d6e9fe260f5c0be81d0ce672 Signed-off-by:
Spencer Oliver <spen@spen-soft.co.uk>
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Vincent Palatin authored
Add the identifiers to support the flash on the Cypress Type-C Port Controller chips of the CCG1 family : http://www.cypress.com/ccg1/ . Tested successfully on CYPD1132-16SXI. Change-Id: I3fe6283379e5bcab964afac31b547ef95535aa2c Signed-off-by:
Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://openocd.zylin.com/2757 Tested-by: jenkins Reviewed-by:
Tomas Vanek <vanekt@fbl.cz> Reviewed-by:
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Peter A. Bigot authored
The notation Gx0 in the nRF51 Series Compatibility Matrix indicates that the specified HWID is valid only for build code 0 of each chip, and for subsequent builds the HWID will be different. Replace the Gx0 notation with G0 throughout, and add the missing HWID for nRF51422 QFAC A1 (present on the newer nRF51 developer boards). See: https://www.nordicsemi.com/eng/nordic/download_resource/41917/5/55913589 See: https://devzone.nordicsemi.com/question/30774/mapping-hwid-to-revision-information/ Change-Id: I79d842137d41342db35904867c48b06fbc6fbc70 Signed-off-by:
Peter A. Bigot <pab@pabigot.com> Signed-off-by:
Angus Gratton <gus@projectgus.com> Reviewed-on: http://openocd.zylin.com/2593 Tested-by: jenkins Reviewed-by:
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Karl Palsson authored
This has been the case since c6216201 in 2013 Signed-off-by:
Karl Palsson <karlp@tweak.net.au> Change-Id: I70232a46e29951f05f02dec00e0695d761697aa5 Reviewed-on: http://openocd.zylin.com/2764 Tested-by: jenkins Reviewed-by:
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Austin Morton authored
Since commit 1d0cf0df ("server: tcl_notifications command") connecting to the tcl server would terminate openocd. Fix this. Change-Id: I36e2a7482f7db3a30ff7e9f969c3b6cda9599382 Signed-off-by:
Austin Morton <austinpmorton@gmail.com> Reviewed-on: http://openocd.zylin.com/2759 Tested-by: jenkins Reviewed-by:
Forest Crossman <cyrozap@gmail.com> Reviewed-by:
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Paul Fertser authored
Change-Id: Ie7fbb9f87a811c4add5b7c8f9581d5bbc90fa4f8 Signed-off-by:
Andreas Fritiofson <andreas.fritiofson@gmail.com>
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Paul Fertser authored
Change-Id: If3fbb2fe4f1842bea3962a6b903fd16aa9e8b545 Signed-off-by:
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Paul Fertser authored
HID and composite devices need to be mentioned explicitly due to windows oddities. Change-Id: I7cdbaa50c60ceb1950c934e0249986d46c875cff Signed-off-by:
Xiaofan <xiaofanc@gmail.com> Reviewed-by:
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Paul Fertser authored
Put all the individual driver descriptions to where they really belong, fix sectioning etc. Change-Id: I94dc09e9a296ec57db4475f8dfb0a7d62a754aa4 Signed-off-by:
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Paul Fertser authored
Change-Id: Id84f16de5a3d1907e196d13007a312593bb6670a Signed-off-by:
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Paul Fertser authored
Directory listings are volatile and serve no purpose in the manual. Just remove them. Change-Id: I63d54ba209c29eafb6608cf406b8ce5d8e9ee6c8 Signed-off-by:
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- Apr 24, 2015
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Paul Fertser authored
Signed-off-by: -
Paul Fertser authored
Signed-off-by: -
Paul Fertser authored
Change-Id: I629158b59ff38f9b82a560f119a391bb97af43f2 Signed-off-by:
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Paul Fertser authored
Change-Id: Id3af8dfd18b13947bca4f3c89c2516ccbcef60b6 Signed-off-by:
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Andreas Färber authored
Reset stopped working with this setting. Change-Id: I98e8fafa48e0ab65dce8110870be422edf7b2fdb Signed-off-by:
Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2727 Tested-by: jenkins Reviewed-by:
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Jiri Kastner authored
from TI datasheets for whole cortex-r4 family added JTAG IDs TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns192 0x0B95502F 16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B) http://www.ti.com/lit/pdf/spns230 0x0D8A002F 0x2D8A002F 0x3D8A002F RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns177 0x0D8A002F 0x2D8A002F 0x3D8A002F RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns185 0x0B95502F RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns176 0x0B8A002F 0x2B8A002F 0x3B8A002F RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns182 0x0B95502F RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns184 0x0B95502F TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns186 0x0B97102F RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns180 0x0B97102F RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/ 0x0B95502F TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns191 0x0B95502F RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns175 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns165 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F) http://www.ti.com/lit/pdf/spns141 0x0B7B302F TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns164 0x0B8A002F 0x2B8A002F 0x3B8A002F RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns174 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns162 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns190 0x0B95502F TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns189 0x0B95502F TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns188 0x0B95502F Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c Signed-off-by:
Jiri Kastner <cz172638@gmail.com> Tested-by:
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Alex Ray authored
Split TMS570 target into LS31/LS21 and LS20/LS10 targets. Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI. Tested attaching. Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620 Signed-off-by:
Alex Ray <a@machinaut.com> Reviewed-on: http://openocd.zylin.com/2089 Tested-by: jenkins Reviewed-by:
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Paul Fertser authored
Since mqx comes last in the list, with the auto option its update_threads is called even though it wasn't detected. This check should be removed from all the rtos helpers and moved to the generic code, but better do it later all in one go. Change-Id: If24ab42a58a468d90e9f12028d4c2fb76a9bc2e8 Signed-off-by:
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Paul Fertser authored
It was observed on AM437x that after every reset the target's debug regions are unpowered. To be able to properly communicate with the target and perform cortex_a init debug access after a reset event the examination need to be performed every time, not just on OpenOCD start. Change-Id: Idf272e127ee88341e806ee00df154eade573451d Signed-off-by:
Felipe Balbi <balbi@ti.com>
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Paul Fertser authored
After intermittent connection failures or target power failures it might be necessary to try reexamination even when polling fails. This should make communication with Cortex-A targets more reliable. This was runtime tested with stlink attached to an stm32l1 and an FTDI JTAG adapter attached to an stm32f1 target. Change-Id: I38c4db8124b7f4bbf53ddda53c13273449f49c15 Signed-off-by:
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Paul Fertser authored
Exposed by arm-none-eabi build. Change-Id: I657c642249aa83403f93132d1e28713aee692c30 Signed-off-by:
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- Apr 16, 2015
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Simon Qian authored
Change-Id: I99cdc11ba1442e4c9efaa0f1de8e7089ec725e14 Signed-off-by:
Simon Qian <openocd@versaloon.com> Reviewed-on: http://openocd.zylin.com/2608 Tested-by: jenkins Reviewed-by:
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Andrey Yurovsky authored
This adds support for the new Atmel SAML21 family of low-power Cortex M0+ devices. Their Flash controller is essentially the SAMDxx one so the change consists of adding the new part IDs. Unfortunately the device ID logic had a couple of mistakes in it that did not affect anything on SAMD2x devices (due to 0 values expected there) but that is a problem on L21, it's therefore addressed here and things should now match the datasheets. Tested on Amtel SAML21 Xplained Pro development kit against the included SAML21J18A there. Also tested for regressions on a SAMD20 and SAMD21 using their dev kits. Change-Id: I768f75e064b8656c15148730dacaa4c3acfc4101 Signed-off-by:
Andrey Yurovsky <yurovsky@gmail.com> Reviewed-on: http://openocd.zylin.com/2690 Tested-by: jenkins Reviewed-by:
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Uwe Bonnes authored
Change-Id: I637cb63bd39120554aa184eaa48fd00a4852359f Signed-off-by:
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2706 Tested-by: jenkins Reviewed-by:
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Paul Fertser authored
This adds the mandatory Info documentation for the driver as well as the usage field. As a clean up, this also includes freeing of the allocated memory which results in a memory leak if probe is invoked multiple times. Valgrind-tested. Reported by Dmitry Shpak. Change-Id: I2b1d9b9e8b069c6665b11d880b40ce19a1b26ce6 Signed-off-by:
Дмитрий Шпак <disona@yandex.ru> Reviewed-by:
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Marc Schink authored
This patch was tested with an EZR32WG Starter Kit. Change-Id: I0f7c619e715fe30e88e6da3bead0806dd3bce819 Signed-off-by:
Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2700 Tested-by: jenkins Reviewed-by:
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Spencer Oliver authored
Change-Id: I8b55c8d12773a1c36f2fd2afeecf20a74e890064 Signed-off-by:
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Spencer Oliver authored
Change-Id: Iae7ed8d59a722b805536550a8033f5fb7c85c5fc Signed-off-by:
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Mahavir Jain authored
* also included example for flash usage information Change-Id: Icf9defc25d38bf24567b1708138b83a8de1e0497 Signed-off-by:
Mahavir Jain <mjain@marvell.com> Reviewed-on: http://openocd.zylin.com/2705 Tested-by: jenkins Reviewed-by:
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Paul Fertser authored
Use mmw to manipulate only selected bits of the word. msb and mwb verify the memory location and may error on PLLRDY set as a result of PLLON written. Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d Reported-by:
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Paul Fertser authored
Currently itmdump is not a production-quality code hence this hack seems to be appropriate. More robust handling is possible with libswo-based swodec tool that's available from http://git.zapb.de/ . This adds a new command line option -d N where N is a stimulus number you want to dump (counting from 1). The idea here is that if you're interested to live-monitor just a single stimulus port, you can use this utility directly. If one wants to demultiplex the TPIU stream, the following is proposed: 1. Use https://gitorious.org/multiplex/multiplex utility that can accept binary data from a file/pipe/stdin and arbitrary number of TCP connections. It simply mirrors all the incoming data to all the accepted connections; 2. Use socat to connect itmdump to the proxy mentioned in 1. and then either dump the results to separate files or share via their dedicated TCP ports. Example script (inspired by http://openocd.zylin.com/#/c/1662/ , enables and disables specific itm ports on demand): for i in `seq 0 31`; do while true; do socat -U TCP-LISTEN:$((8000+$i)),reuseaddr \ SYSTEM:"echo itm port $i on | nc -q0 localhost 4444 > /dev/null; nc localhost 7777 | stdbuf -oL itmdump -d$((i+1))" echo itm port $i off | nc -q0 localhost 4444 > /dev/null done < /dev/null >&0 2>&0 & done Change-Id: Iaeb102436eaa5b106002083f2ffe758fb7bd83e5 Signed-off-by:
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Paul Fertser authored
Change-Id: I1fe5c5c0b22cc23deedcf13ad5183c957551a1b7 Signed-off-by:
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Felipe Balbi authored
GP and EPOS EVMs do not provide xds100v2 on board, rather they have a pin header which can be used to attach any debug pod the user might want. Change-Id: I61678c50900fbe0fab500ea42f85ecde7a490ded Reported-by:
Tom Rini <trini@konsulko.com> Signed-off-by:
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Andreas Fritiofson authored
Run-time tested with FreeRTOS V8.1.2 (current version). For the time being I propose this way of dealing with RTOSes that do not export necessary information on their own. I also suggest implementing a similar scheme for ChibiOS, exporting the necessary struct fields' offsets via an OpenOCD-specific helper. Change-Id: Iacf8b88004d62206215fe80011fd7592438446a3 Signed-off-by:
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Andreas Fritiofson authored
xSuspendedTaskList and xTasksWaitingTermination are only available for some configurations. Missing optional symbols will have their addresses remaining at zero so the corresponding lists will be skipped when building the task list. Change-Id: If330f5038d009298c3a14a4d2756db7105a30bc8 Signed-off-by:
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- Apr 14, 2015
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Tomas Vanek authored
This is a remake of http://openocd.zylin.com/1966 originally written by Angus Gratton <gus@projectgus.com> ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU in reset if TCK is low when srst (RESET_N) is deasserted. Without this change any use of sysresetreq or srst locks the chip in reset state until power is cycled. A new function smap_reset_deassert is called as reset-deassert-post event handler. It optionally prepares reset vector catch and SMAP reset is released then. Change-Id: Iad736357b0f551725befa2b9e00f3bc54504f3d8 Signed-off-by:
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Paul Fertser authored
Some targets need arbitrary amount of time (usually not too long) after reset (both sysresetreq and srst) to do initialisation, and SWD/JTAG is not available during that. According to PSoC4 docs, the debugger should try connecting until it succeeds. Also ahbap_debugport_init might be necessary to perform after using hardware srst too, so add it there (except for the targets that support srst_nogate since they are very unlikely to need it). Change-Id: I3598d5ff7b8e0bf3a5566a57dec4b0b2b243d297 Signed-off-by:
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Paul Fertser authored
In some cases (the most obvious are TI's SoCs) ROM table lacks entries for the cores, so OpenOCD has no way to determine what debug base to use. Due to an error fixed in ec9ccaa2 it wasn't handled properly, and OpenOCD would continue to try using dbgbase = 0, which happened to work for e.g. AM437x. This patch adds a clear indication to the user that to access such a target, dbgbase must be set manually in the config. Reported by Felipe Balbi on IRC. Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298 Signed-off-by:
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