pcb.py

#
# define board
#

width = 1.02 # board width
height = .87 # board height
x = 1 # x origin
y = 1 # y origin
zt = 0 # top z
zb = -0.06 # bottom z
w = .015 # wire width
rv = 0.016 # via size
rp = 0.03 # pad size
mask = .004 # solder mask size

pcb = PCB(x,y,width,height,mask)

IC1 = ATtiny44_SOICN('IC1\nt44')
pcb = IC1.add(pcb,x+.49,y+.56)

VIC1 = via(zb,zt,rv,rp)
pcb = VIC1.add(pcb,IC1.pad[14].x+.08,IC1.pad[14].y+.02)

pcb = wire(pcb,w,
   VIC1.pad[1],
   IC1.pad[14])

J1 = header_ISP('J1\nISP')
pcb = J1.add(pcb,IC1.x+.05,IC1.pad[7].y-.22,angle=90)

pcb = wire(pcb,w,
   IC1.pad[8],
   point(J1.pad[1].x,IC1.pad[8].y),
   J1.pad[1])

pcb = wire(pcb,w,
   IC1.pad[9],
   point(J1.pad[3].x,IC1.pad[9].y),
   J1.pad[3])
   
pcb = wire(pcb,w,
   IC1.pad[7],
   point(IC1.pad[7].x,J1.y+.02),
   point(IC1.pad[7].x+.04,J1.y-.02),
   point(J1.pad[4].x,J1.y-.02),
   J1.pad[4])
   
pcb = wire(pcb,w,
   IC1.pad[4],
   point(J1.pad[5].x,IC1.pad[4].y),
   J1.pad[5])

VJ12 = via(zb,zt,rv,rp)
pcb = VJ12.add(pcb,J1.pad[2].x+.075,J1.pad[2].y)

pcb = wire(pcb,w,
   VJ12.pad[1],
   J1.pad[2])

VJ16 = via(zb,zt,rv,rp)
pcb = VJ16.add(pcb,J1.pad[6].x-.075,J1.pad[6].y)

pcb = wire(pcb,w,
   VJ16.pad[1],
   J1.pad[6])

pcb = wire(pcb,w,
   VJ16.pad[2],
   VIC1.pad[2])

J2 = header_FTDI('J2 FTDI')
pcb = J2.add(pcb,x+width-.22,IC1.y-.0,angle=0)

pcb = wire(pcb,w,
   IC1.pad[13],
   point(IC1.pad[13].x+.105,IC1.pad[13].y),
   point(IC1.pad[13].x+.105,J2.pad[4].y),
   J2.pad[4])

pcb = wire(pcb,w,
   IC1.pad[12],
   point(IC1.pad[12].x+.07,IC1.pad[12].y),
   point(IC1.pad[12].x+.07,J2.pad[5].y+.04),
   point(IC1.pad[12].x+.11,J2.pad[5].y),
   J2.pad[5])

VJ2 = via(zb,zt,rv,rp)
pcb = VJ2.add(pcb,J2.pad[3].x+.1,J2.pad[3].y)

pcb = wire(pcb,w,
   VJ2.pad[1],
   J2.pad[3])

pcb = wire(pcb,w,
   VJ12.pad[2],
   VJ2.pad[2])

XTAL1 = XTAL_EFOBM('XTAL1\n20 MHz')
pcb = XTAL1.add(pcb,IC1.pad[4].x-.2,IC1.pad[13].y+.003,angle=-90)

pcb = wire(pcb,w,
   IC1.pad[2],
   point(XTAL1.x+.12,IC1.pad[2].y),
   point(XTAL1.x+.12,XTAL1.pad[1].y),
   XTAL1.pad[1])

pcb = wire(pcb,w,
   IC1.pad[3],
   XTAL1.pad[3])

VXTAL = via(zb,zt,rv,rp)
pcb = VXTAL.add(pcb,XTAL1.x-.12,XTAL1.y)

pcb = wire(pcb,w,
   XTAL1.pad[2],
   VXTAL.pad[1])

pcb = wire(pcb,w,
   VJ16.pad[2],
   VXTAL.pad[2])

R1 = R_1206('R1\n10k');
pcb = R1.add(pcb,IC1.pad[1].x,IC1.pad[1].y+.1)

pcb = wire(pcb,w,
   R1.pad[1],
   IC1.pad[1])

pcb = wire(pcb,w,
   R1.pad[2],
   point(J1.pad[5].x,R1.y),
   J1.pad[5])

VR1 = via(zb,zt,rv,rp)
pcb = VR1.add(pcb,R1.pad[1].x-.08,R1.y)

pcb = wire(pcb,w,
   VR1.pad[1],
   R1.pad[1])

pcb = wire(pcb,w,
   VJ2.pad[2],
   point(VJ2.x,VR1.y,zb),
   VR1.pad[2])

C1 = C_1206('C1\n1uF');
pcb = C1.add(pcb,IC1.pad[14].x,R1.y)

pcb = wire(pcb,w,
   J2.pad[1],
   C1.pad[2])

pcb = wire(pcb,w,
   C1.pad[2],
   VIC1.pad[1])

VC1 = via(zb,zt,rv,rp)
pcb = VC1.add(pcb,C1.pad[1].x-.025,C1.y-.06)

pcb = wire(pcb,w,
   VC1.pad[1],
   C1.pad[1])

pcb = wire(pcb,w,
   VR1.pad[2],
   point(VC1.x,VR1.y,zb),
   VC1.pad[2])

#
# select output
#

outputs = {}
if (output == "top, labels, and exterior"):
   outputs["function"] = add(add(color(Tan,pcb.board),pcb.labels),
      color(White,pcb.exterior))
   outputs["layers"] = [zt]
elif (output == "top, bottom, labels, and exterior"):
   outputs["function"] = add(add(color(Tan,pcb.board),pcb.labels),
      color(White,pcb.exterior))
   outputs["layers"] = [zb,zt]
elif (output == "top, bottom, labels, holes, and exterior"):
   outputs["function"] = add(add(color(Tan,
      subtract(pcb.board,pcb.holes)),pcb.labels),
      color(White,pcb.exterior))
   outputs["layers"] = [zb,zt]
elif (output == "top traces"):
   outputs["function"] = color(White,pcb.board)
   outputs["layers"] = [zt]
elif (output == "top traces and exterior"):
   outputs["function"] = color(White,add(pcb.board,pcb.exterior))
   outputs["layers"] = [zt]
elif (output == "bottom traces reversed"):
   outputs["function"] = color(White,
      reflect_x(pcb.board,2*x+width))
   outputs["layers"] = [zb]
elif (output == "bottom traces reversed and exterior"):
   outputs["function"] = color(White,
      reflect_x(add(pcb.board,pcb.exterior),2*x+width))
   outputs["layers"] = [zb]
elif (output == "interior"):
   outputs["function"] = color(White,pcb.interior)
   outputs["layers"] = [zb]
elif (output == "exterior"):
   outputs["function"] = color(White,pcb.exterior)
   outputs["layers"] = [zb]
elif (output == "holes"):
   outputs["function"] = color(White,
      subtract(add(pcb.exterior,pcb.interior),pcb.holes))
   outputs["layers"] = [zb]
elif (output == "holes and interior"):
   outputs["function"] = color(White,
      subtract(pcb.interior,pcb.holes))
   outputs["layers"] = [zb]
elif (output == "solder mask"):
   outputs["function"] = color(White,pcb.mask)
   outputs["layers"] = [zt]
else:
   print("oops -- don't recognize output")

#
# set limits and parameters
#

border = 0.05
outputs["xmin"] = x-border # min x to render
outputs["xmax"] = x+width+border # max x to render
outputs["ymin"] = y-border # min y to render
outputs["ymax"] = y+height+border # max y to render
outputs["mm_per_unit"] = 25.4 # use inch units
outputs["type"] = "RGB" # use RGB color

#
# send output
#

json.dump(outputs,sys.stdout)